Elenco Electronics MO-1251 Instrukcja Użytkownika Pobierz pdf (Strona 57)

14

13

1!,

v

h l

IC1

4017B

CLK

ENABLE

Rf',f

L'.1!

DO 0

DO

1

DO 2

DO

3

DO

4

DO 5

DO 6

DO 7

DO 8

DO 9

3

4

10

5

6

9

11

CARRY

12

OUT

WORKING

WITH

COUNTERS

FIG.

1 -THE 40176 DECADE

COUNTER

has 10 DECODED OUTPUTS, a CARRY OUT bit,

and

is

triggered on the clock's

rising -

edge.

CMOS D AND

JK FLIP -FLOPS ARE

THE BUILD

-

ing blocks for

all counter /dividers.

Constructing your own

counter /divid-

er

is fine

-especially when

only one

or two flip -flops

are required.

How-

ever, for

a complicated design requir-

ing 10

or more flip -flops,

it's best to

use a

counter

/divider

IC

already de-

veloped

in

a

single

Dual In

-line Pack-

age

(DIP): options include

binary,

decade,

or hexadecimal

counters, up/

down counting,

resets, presets,

LED

driver outputs,

and a carry-out line for

cascading

IC's. Let's start

by examin-

ing one of

the best know

CMOS up-

counters,

the

4017B.

Decade

counter

Figure

1 shows

the

40I7B

IC

pin

-

out;

that IC is one

of the best known

CMOS up-

counters, having

a

syn-

chronous

decade -counter and 10 -de-

coded

outputs.

Synchronous means

that

all

flip -flops

are triggered at the

same

time (no ripple

through clock-

ing),

and all DECODED OUTPUTS

0 -9

will

change states

simultaneously.

The

4017B

works quite

simply: When

as-

serted,

a

single

high bit is

latched into

the counter

at DECODED OUTPUT O.

That

bit will

then travel

to the next DECODED

OUTPUT on

the rising

edge of each new

CLOCK

ENABLE

RESET

CLOCK

INPUT

DECODED

OUTPUT o

DECODED OUTPUT

1

DECODED

OUTPUT 2

DECODED

OUTPUT

3

DECODED

OUTPUT

4

DECODED

OUTPUT 5

DECODED

OUTPUT 6

DECODED

OUTPUT

7

DECODED

OUTPUT 8

DECODED

OUTPUT 3

CARRY

OUT

Count on

counter

circuits

to keep

counting.

RAY

MARSTON

1

2

3

4

5

6

7

8 9

10 11 12

13

2

ft

f L

r7 r

1 a

1

5

6

n

RG.

2- TIMING DLß.GRAM

OF

THE 4017B.

Only one DECODED OUTPUT is

high

at any given

mcment.

clock pulse.

(Only one

of the ten

DECODED

OUTPUTS will

be high

at any

given

moment.)

The DECODED

OUT-

PUTS 0 -9

thereby represent

a decimal

(1 -10)

equivalent of

the total number

of clock

cycles.

Timing

diagrams

the tinting

diagram

for any

counter

IC is like

a road

map -without

it you

will

be lost. If you

intend

to do

any

serious

design work

using

counter

ICs,

then by all means get

a copy of

National

Semiconductor's

CMOS

logic

data

book.

Figure 2 shows the 4017B timing

diagram.

By placing a high

on

the

RESET

(pin 15) and holding

the

CLOCK

ENABLE (pin 13) low,

the chip is as-

serted

and a high bit is automatically

entered into DECODED OUTPUT 0 (pin

9).

To initialize

the IC, the RESET line

should

be brought low

just

after the

rising -edge of the first

clock pulse.

On the rising

edge of the second clock

pulse,

the high bit

will

then advance

to DECODED OUTPUT

I (pin 2). Then,

after the rising

edge of the third clock

pulse, the high bit will

advance to

DECODED

OUTPUT

2

(pin 4), and so

forth.

At any given moment, nine of

the ten DECODED OUTPUTS will be low,

with

the remaining DECODED OUTPUT

high. The

counting cycle can be

63

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 99 100

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